The subject matter described herein relates generally to semiconductor processing, and more particularly to lithography masks.
Line-ends are generally structures of a semiconductor layer design that are highly susceptible to process variations including focus variations, dose variations and variations in mask making. The sensitivity to mask size variations is especially problematic. For example, spaces facing each other at tight chrome separation on a photomask suffer from significant pullback. Moreover, there is significant variability of the minimum end-to-end structure due to high MEEF (mask edge error factor), which may result in poor pattern fidelity and inability to meet tight design rules. The current state of the art depends on other MEEF-mitigation schemes like high NA, resolution enhancement techniques, etc. to control the problem, with limited success. Patterning of such end-to-end structures is a key limiter for design-rule scaling.